1. Field of the Invention
The present invention relates to a multiplexer, and particularly a multiplexer which converts parallel data signals of multiple bits into a serial data signal of multiple bits in synchronization with a clock signal.
2. Description of the Background Art
FIG. 9 is a block diagram showing a structure of a multiplexer in the prior art. Referring to FIG. 9, the multiplexer includes a quarter divider 31, a control signal generating circuit 32, D-flip-flops 33-36 and 38, and a four-to-one selector 37.
As shown in FIG. 10, quarter divider 31 includes a D-flip-flop 41, and also include D-latches 42 and 43 which form a D-flip-flop 44. Flip-flop 41 and latch 42 are of a negative edge type, and therefore issue data in response to a falling edge of a clock signal. Latch 43 is of a positive edge type, and therefore issues data in response to the rising edge of clock signal.
Flip-flop 41 receives clock signal CLK on its clock terminal C, and have an output terminal Q and an inverted output terminal QB which are connected to an inverted input terminal DB and an input terminal D, respectively. Accordingly, flip-flop 41 issues from its output terminal Q a clock signal CLK/2, which has half a frequency of clock signal CLK, and is inverted upon every falling of clock signal CLK.
Clock signal CLK/2 is applied to clock terminals C of latches 42 and 43. Output terminal Q and inverted output terminal QB of latch 42 are connected to input terminal D and inverted input terminal DQ of latch 43, respectively. Output terminal Q and inverted output terminal QB of latch 43 are connected to inverted input terminal DB and input terminal D of latch 42, respectively. Accordingly, latches 42 and 43 issue clock signals xcfx861-xcfx864, which have four phases shifted from each other by xc2xc of their period, respectively, and each have a frequency equal to xc2xc of that of clock signal CLK. Clock signals xcfx861-xcfx864 are supplied to control signal generating circuit 32. Output signal xcfx862 (CLK/4) of latch 43 is applied to clock terminals C of flip-flops 33-36.
Control signal generating circuit 32 includes four NOR gates 51-54 and four NAND gates 55-58. Each of NOR gates 51-54 receives signals of two phases among clock signals xcfx861-xcfx864, and issues corresponding one of control signals S1-S4. Each of NAND gates 55-58 receives signals of two phases among clock signals xcfx861-xcfx864, and issues corresponding one of control signals S1B-S4B. Control signals S1-S4 have frequencies equal to that of clock signal CLK/4, and successively attain xe2x80x9cHxe2x80x9d level for xc2xc of the period. Signals S1B-S4B are inverted signals of signals S1-S4, respectively. Control signals S1-S4 and S1B-S4B are applied to four-to-one selector 37. In FIG. 9, signals S1B-S4B are not shown for simplicity reason.
Flip-flops 33-36 receive data D1-D4 on their input terminals D, and also receive clock signal CLK on their clock terminals C, respectively. Flip-flops 33-36 are of the negative edge type, and issue input data D1-D4 in response to the falling edge of clock signal CLK/4. Output data D1xe2x80x2-D4xe2x80x2 of flip-flops 33-36 are applied to four-to-one selector 37.
Four-to-one selector 37 includes, as shown in FIG. 11, four input nodes N1-N4, four transfer gates 61-64 and an output node N5. Four input nodes N1-N4 are supplied with output data D1xe2x80x2-D4xe2x80x2 of flip-flops 33-36, respectively. Transfer gates 61-64 are connected between input nodes N1-N4 and output node N5, respectively, and are turned on in response to the states that control signals S1-S4 attain xe2x80x9cHxe2x80x9d level and control signals S1B-S4B attain xe2x80x9cLxe2x80x9d level, respectively. Accordingly, data D1xe2x80x2-D4xe2x80x2 are issued to output node N5 in response to the states that control signals S1-S4 attain xe2x80x9cHxe2x80x9d level and control signals S1B-S4B attain xe2x80x9cLxe2x80x9d level, respectively.
An output data SOUT of selector 37 is supplied to input terminal D of flip-flop 38, which also receives clock signal CLK on its clock terminal C. Flip-flop 38 is of a negative edge type, and issues input data SOUT in response to the falling edge of clock signal CLK. The output data of flip-flop 38 forms output data DOUT of this multiplexer.
FIGS. 12A-12H are time charts showing operations of the multiplexer shown in FIGS. 9 to 11. Quarter divider 31 produces a clock signal CLK/4 having a period four times larger than that of clock signal CLK. Clock signal CLK/4 is applied to clock terminals C of flip-flops 33-36. Flip-flops 33-36 continuously issue the same data D1xe2x80x2-D4xe2x80x2 for one period of clock signal CLK/4 (during cycles 1 to cycle 4 in FIG. 12).
Quarter divider 31 produces four clock signals xcfx861-xcfx864 which have the same frequencies as clock signal CLK/4, and also have phases shifted from each other by a quarter of the period. Clock signals xcfx861-xcfx864 are applied to control signal generating circuit 32. Control signals generating circuit 32 produces control signals S1-S4 which attain xe2x80x9cHxe2x80x9d level in cycles 1-4, respectively, as well as inverted signals S1B-S4B of them, and applies signals S1-S4 and S1B-S4B to a selector 37.
Transfer gates 61-64 of selector 37 are turned on during cycles 1-4 in accordance with S1 and S1B, . . . , and S4 and S4B, respectively. Accordingly, data D1_1-D4_1 corresponding to data D1xe2x80x2-D4xe2x80x2 are issued in serial from output node N5 of selector 37 to flip-flop 38 at every clock cycle, respectively.
Flip-flop 38 issues input data D1_1-D4_1 in response to the falling edges of cycles 2 to 5, respectively. In this manner, slow parallel data D1-D4 are converted into fast serial data D1_1-D4_4.
FIGS. 12A-12H are time charts showing the operations in the case where each circuit included in the multiplexer does not have a delay time. However, each circuit included in the multiplexer practically has a delay time. Since quarter divider 31 has two flip-flops 41 and 44, quarter divider 31 has the delay time of 2T_DFF equal to double the delay time T_DFF of each flip-flop. As shown in FIGS. 13A-13D, therefore, the phase of dock signal CLK_4 is delayed by 2T_DFF from clock signal CLK.
The delay time of control signal generating circuit 32 is equal to a delay time T_NOR of an NOR gate because the delay time of the NOR gate is generally longer than that of an NAND gate. Accordingly, the phases of control signals S1-S4 are delayed from clock signal CLK by (2T_DFF+T_NOR).
Assuming that selector 37 has a delay time of T_sel, a time of (2T_DFF+T_NOR+T_sel) is required from the input of clock signal CLK to the output from selector 37, and a setup time T_setup of flip-flop 38 is required for taking in output data SOUT of selector 37 into flip-flop 38. Therefore, a time of (2T_DFF+T_NOR+T_sel+T_setup) must fall within one clock cycle.
Accordingly, the multiplexer suffers from a problem that the maximum operation frequency fmax is restricted to or below the following value:
fmax=1/(2T_DFF+T_NOR+T_sel+T_setup)xe2x80x83xe2x80x83(1)
Accordingly, a major object of the invention is to provide a fast-operating multiplexer, i.e., a multiplexer which can operate fast.
According to an aspect of the invention, a multiplexer includes a signal generating circuit for generating control signals of M phases, a first holding circuit for temporarily holding the control signals of M phases, and thereafter issuing the control signals in synchronization with a clock signal, a select circuit for converting parallel data signals of M bits into a serial data signal of M bits in response to the control signals of M phases, and a second holding circuit for temporarily holding each of output signals of the select circuit, and thereafter issuing the output signal of the select circuit in synchronization with the clock signal. Accordingly, it is merely required that a sum of a delay time of the signal generating circuit and a setup time of the first holding circuit falls within one clock cycle. Therefore, the operation speed can be higher than that in the prior art not provided with the first holding circuit.
Preferably, the signal generating circuit includes an internal clock generating circuit for producing internal clock signals of M phases, and a logic circuit for producing the control signals of M phases based on the internal clock signals of M phases. Each of the control signals is at a first level during (1/M) of one period, and is at a second level during (Mxe2x88x921)/M of one period. This allows easy production of the control signals of M phases, and thus allows easy control of the select circuit.
More preferably, the multiplexer further includes a third holding circuit for temporarily holding the internal clock signals of M phases issued from the internal clock generating circuit, and issuing the internal clock signals to the logic circuit in synchronization with the clock signal. In this case, it is merely required that a sum of the delay times of the third holding circuit and the logic circuit and the setup time of the first holding circuit fall within one clock cycle. Accordingly, the operation speed can be further increased.
Preferably, the multiplexer further includes a first delay circuit for delaying the clock signal. The first and second holding circuits operate in synchronization with the clock signal delayed by the first delay circuit. In this case, timing margins before and after the signal generating circuit can be increased so that the operation speed can be further increased.
Preferably, the multiplexer further includes first and second delay circuits for delaying the clock signal. The first holding circuit operates in synchronization with the clock signal delayed by the first delay circuit, and the second holding circuit operates in synchronization with the clock signal delayed by the first and second delay circuits. In this case, timing margins before and after the select circuit can be increased so that the operation speed can be further increased.
Preferably, the multiplexer further includes first, second and third delay circuits for delaying the clock signal. The third holding circuit operates in synchronization with the clock signal delayed by the first delay circuit. The first holding circuit operates in synchronization with the clock signal delayed by the first and second delay circuits. The second holding circuit operates in synchronization with the clock signal delayed by the first to third delay circuits. In this case, it is possible to increase the timing margins before and after the internal clock generating circuit so that the operation speed can be further increased.
According to another aspect of the invention, a device includes a first signal converting circuit for converting parallel data signals of (Mxc3x97N) bits into first to Mth parallel data signal columns, and a second signal converting circuit for converting the first to Mth parallel data signal columns into a serial data signal of (Mxc3x97N) bits. The second signal converting circuit includes a first signal generating circuit for producing first control signals of M phases, a first holding circuit for temporarily holding the first control signals of M phases, and thereafter issuing the first control signals in synchronization with the clock signal, a first select circuit for converting the first to Mth parallel data signal columns into a serial data signal of (Mxc3x97N) bits in response to the first control signals of M phases, and a second holding circuit for temporarily holding each of the output data signals of the first select circuit, and thereafter issuing the output data signal of the first select circuit in synchronization with the clock signal. Accordingly, it is merely required that the sum of the delay time of the first signal generating circuit and the setup time of the first holding circuit fall within one clock cycle. Therefore, the operation speed can be faster than that in the prior art not provided with the first holding circuit. Between the first and second signal generating circuits, only the second signal generating circuit is required to operate fast, and the first holding circuit is added only to this second signal generating circuit. Therefore, increase in power consumption can be minimized.
Preferably, the first signal generating circuit includes an internal clock generating circuit for producing internal clock signals of M phases, and a logic circuit for producing the first control signals of M phases based on the internal clock signals of M phases. Each of the first control signals is at a first level during (1/M) of one period, and is at a second level during (Mxe2x88x921)/M of one period. This allows easy production of the first control signals of M phases, and thus allows easy control of the first select circuit.
More preferably, the multiplexer further includes a third holding circuit for temporarily holding the internal clock signals of M phases issued from the internal clock generating circuit, and issuing the internal clock signals to the logic circuit in synchronization with the clock signal. In this case, it is merely required that a sum of the delay times of the third holding circuit and the logic circuit and the setup time of the first holding circuit fall within one clock cycle. Accordingly, the operation speed can be further increased.
Preferably, the internal clock signal of one phase among the internal clock signals of M phases is selected as a reference clock signal, and the first signal converting circuit includes a second signal generating circuit for producing second control signals of N phases, a fourth holding circuit for temporarily holding the second control signals of N phases, and thereafter issuing the second control signal in synchronization with the reference clock signal, a second select circuit for converting the parallel data signals of (Mxc3x97N) bits into the first to Mth parallel data signal columns in response to the second control signal of the N phases, and a fifth select circuit for temporarily holding each data signal of the second select circuit at a time, and thereafter issuing the held output data signal in synchronization with the clock signal. Therefore, it is merely required that a sum of the delay time of the second signal generating circuit and the setup time of the fourth holding circuit fall within M clock cycles. Accordingly, the operation speed can be higher than that in the prior art not provided with a fourth holding circuit.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.